Low-Power Wireless SoC Architect

<div class="field f-n-body f-t-text-with-summary"><h2>Job description</h2> <p style="text-align: justify;"><strong><em>This role does not offer any hybrid/remote work possibility.</em></strong></p> <p style="text-align: justify;">The Low-Power Wireless SoC Architect owns the system and digital architecture of next-generation ultra-low-power wireless SoCs from product requirements through production. This is primarily a digital ASIC architecture role—not an RF architecture role—and requires strong understanding of embedded software, memory, security, test, analog/RF interfaces, and manufacturing.</p> <p><strong>Key Responsibilities</strong></p> <ul> <li>Own the digital SoC architecture: processor, interconnect, memory hierarchy, clock/reset, power domains and modes, peripherals, security, debug, test, and hardware/software partitioning</li> <li>Translate product requirements into architecture specifications, interfaces, verification objectives, and measurable power, performance, area, cost, and risk budgets</li> <li>Drive digital ASIC decisions covering IP selection and reuse, RTL architecture, low-power intent, CDC/RDC, DFT, implementation constraints, and design-for-verification</li> <li>Align Digital Design, Verification, IC Integration, software, validation, test, memory, analog/RF, CAD/PDK, package, and manufacturing contributors</li> <li>Lead architecture reviews and formal change control; support implementation, tape-out, silicon bring-up, qualification, yield improvement, and production issue resolution</li> </ul> </div>